philips semiconductors application note AN189 balanced modulator/demodulator applications using the mc1496/1596 1 1988 may rev 1. 1993 dec balanced modulator/demodulator applications using mc1496/mc1596 the mc1496 is a monolithic transistor array arranged as a balanced modulator-demodulator . the device takes advantage of the excellent matching qualities of monolithic devices to provide superior carrier and signal rejection. carrier suppressions of 50db at 10mhz are typical with no external balancing networks required. applications include am and suppressed carrier modulators, am and fm demodulators, and phase detectors. theory of operation as figure 1 suggests, the topography includes three dif ferential amplifiers. internal connections are made such that the output becomes a product of the two input signals v c and v s . to accomplish this the dif ferential pairs q1-q2 and q3-q4, with their cross-coupled collectors, are driven into saturation by the zero crossings of the carrier signal v c . with a low level signal, v s driving the third dif ferential amplifier q5-q6, the output voltage will be full wave multiplication of v c and v s . thus for sine wave signals, v out becomes: v out e x e y cos( x y)t cos( x y)t (1) as seen by equation (1) the output voltage will contain the sum and dif ference frequencies of the two original signals. in addition, with the carrier input ports being driven into saturation, the output will contain the odd harmonics of the carrier signals. (see figure 4.) 500 note: all resistor values are in ohms 500 500 carrier input signal input bias v gain adjust 2 3 14 5 1 4 10 6 12 8 () (+) () (+) q1 q2 q3 q4 q5 q6 q7 q8 d1 r1 r3 r2 v o (+) v o () sr00774 figure 1. balanced modulator schematic internally provided with the device are two current sources driven by a temperature-compensated bias network. since the transistor geometries are the same and since v be matching in monolithic devices is excellent, the currents through q 7 and q 8 will be identical to the current set at pin 5. figures 2 and 3 illustrate typical biasing arrangements from split and single-ended supplies, respectively . of primary interest in beginning the bias circuitry design is relating available power supplies and desired output voltages to device requirements with a minimum of external components. the transistors are connected in a cascode fashion. therefore, suf ficient collector voltage must be supplied to avoid saturation if linear operation is to be achieved. v oltages greater than 2v are sufficient in most applications. biasing is achieved with simple resistor divider networks as shown in figure 3. this configuration assumes the presence of symmetrical supplies. explaining the dc biasing technique is probably best accomplished by an example. thus, the initial assumptions and criteria are set forth: 1. output swing greater than 4v p-p . 2. positive and negative supplies of 6v are available. 3. collector current is 2ma. it should be noted here that the collec - tor output current is equal to the current set in the current sources. as a matter of convenience, the carrier signal ports are referenced to ground. if desired, the modulation signal ports could be ground referenced with slight changes in the bias arrangement. with the carrier inputs at dc ground, the quiescent operating point of the outputs should be at one-half the total positive voltage or 3v for this case. thus, a collector load resistor is selected which drops 3v at 2ma or 1.5k w . a quick check at this point reveals that with these loads and current levels the peak-to-peak output swing will be greater than 4v . it remains to set the current source level and proper biasing of the signal ports. the voltage at pin 5 is expressed by v bias v be 500 i s where i s is the current set in the current sources. v cc r l r l r s r s r s r s r 3 r 2 r 1 gain select 500 500 500 note: all resistor values are in ohms sr00775 figure 2. single-supply biasing biasing since the mc1496 was intended for a multitude of dif ferent functions as well as a myriad of supply voltages, the biasing techniques are specified by the individual application. this allows the user complete
philips semiconductors application note AN189 balanced modulator/demodulator applications using the mc1496/1596 1988 may 2 freedom to choose gain, current levels, and power supplies. the device can be operated with single-ended or dual supplies. +6v 1.5k 1.5k 2.2k gain select 500 500 500 note: all resistor values are in ohms -6v 2.2k r s r s r s r s sr00776 figure 3. dual supply biasing v bias = v be = 500 i s where i s is the current set in the current sources. for the example v be is 700mv at room temperature and the bias voltage at pin 5 becomes 1.7v. because of the cascode configuration, both the collectors of the current sources and the collectors of the signal transistors must have some voltage to operate properly . hence, the remaining voltage of the negative supply (6v+1.7v=4.3v) is split between these transistors by biasing the signal transistor bases at 2.15v . countless other bias arrangements can be used with other power supply voltages. the important thing to remember is that suf ficient dc voltage is applied to each bias point to avoid collector saturation over the expected signal wings. balanced modulator in the primary application of balanced modulation, generation of double sideband suppressed carrier modulation is accomplished. due to the balance of both modulation and carrier inputs, the output, as mentioned, contains the sum and dif ference frequencies while attenuating the fundamentals. upper and lower sideband signals are the strongest signals present with harmonic sidebands being of diminishing amplitudes as characterized by figure 4. gain of the 1496 is set by including emitter degeneration resistance located as r e in figure 5. degeneration also allows the maximum signal level of the modulation to be increased. in general, linear response defines the maximum input signal as vs 15 ? r e (peak) and the gain is given by a vs r l r e 2r e (2) this approximation is good for high levels of carrier signals. t able 1 summarizes the gain for different carrier signals. as seen from table 1, the output spectrum suffers an amplitude increase of undesired sideband signals when either the modulation or carrier signals are high. indeed, the modulation level can be increased if r e is increased without significant consequence. however , large carrier signals cause odd harmonic sidebands (figure 4) to increase. at the same time, due to imperfections of the carrier waveforms and small imbalances of the device, the second harmonic rejection will be seriously degraded. output filtering is often used with high carrier levels to remove all but the desired sideband. the filter removes unwanted signals while the high carrier level guards against amplitude variations and maximizes gain. broadband modulators, without benefit of filters, are implemented using low carrier and modulation signals to maximize linearity and minimize spurious sidebands. notes: nf c nf s carrier harmonic sidebands nf c carrier harmonics f c nf s fundamental carrier sideband harmonics f c f s fundamental carrier sidebands f s modulating signal f c carrier fundamental frequency amplitude (f - 2f ) c s (f ) c (f + 2f ) c s (f - f ) c s (f + f ) c s (2f - 2f ) c s (2f - f ) c s (2f ) c (2f + f ) c s (2f + 2f ) c s (3f - 2f ) c s (3f - f ) c s (3f ) c (3f + f ) c s (3f + 2f ) c s sr00777 figure 4. modulator frequency spectrum
philips semiconductors application note AN189 balanced modulator/demodulator applications using the mc1496/1596 1988 may 3 am modulator the basic current of figure 5 allows no carrier to be present in the output. by adding offset to the carrier differential pairs, controlled amounts of carrier appear at the output whose amplitude becomes a function of the modulation signal or am modulation. as shown, the carrier null circuit is changed from figure 5 to have a wider range so that wider control is achieved. all connections are shown in figure 6. am demodulation as pointed out in equation 1, the output of the balanced mixer is a cosine function of the angle between signal and carrier inputs. further , if the carrier input is driven hard enough to provide a switching action, the output becomes a function of the input amplitude. thus the output amplitude is maximum when there is 0 phase difference as shown in figure 7. amplifying and limiting of the am carrier is accomplished by if gain block providing 55db of gain or higher with limiting of 400 m v. the limited carrier is then applied to the detector at the carrier ports to provide the desired switching function. the signal is then demodulated by the synchronous am demodulator (1496) where the carrier frequency is attenuated due to the balanced nature of the device. care must be taken not to overdrive the signal input so that distortion does not appear in the recovered audio. maximum conversion gain is reached when the carrier signals are in phase as indicated by the phase-gain relationship drawn in figure 7. output filtering will also be necessary to remove high frequency sum components of the carrier from the audio signal. phase detector the versatility of the balanced modulator or multiplier also allows the device to be used as a phase detector . as mentioned, the output of the detector contains a term related to the cosine of the phase angle. t wo signals of equal frequency are applied to the inputs as per figure 8. the frequencies are multiplied together producing the sum and dif ference frequencies. equal frequencies cause the dif ference component to become dc while the undesired sum component is filtered out. the dc component is related to the phase angle by the graph of figure 9. 1k 1k +12vdc 1k 51 8 10 1 4 14 5 12 6 3 2 3.9k 3.9k carrier input modulating signal input 10k 50k 10k 51 51 carrier null v 8vdc 6.8k mc1496 note: all resistor values are in ohms 0.1 m f 0.1 m f r e r l r l i 5 +v o v o v c v s sr00778 figure 5. double suppressed carrier modulator table 1. voltage gain and output vs input signal carrier input signal (v c ) approximate voltage gain output signal frequency(s) f c + f m , 3f c + f m . 5f c + f m ... f m f m low-level dc high-level dc low-level ac high-level ac 0.637r l r e 2r e r l v c (rms) 2 2 kt q (r e 2r e ) r l r 2r e r l v c 2(r e 2r e ) kt q f c + f m
philips semiconductors application note AN189 balanced modulator/demodulator applications using the mc1496/1596 1988 may 4 1k 1k +12vdc 1k 51 8 10 1 4 14 5 12 6 3 2 3.9k 3.9k carrier input modulating signal input 750 50k 750 51 51 carrier adjust v 8vdc 6.8k mc1496k note: all resistor values are in ohms 0.1 m f 0.1 m f r e r l r l i 5 +v o v o v c v s mc1596k sr00779 figure 6. am modulator note: all resistor values are in w . +12v .1 .1 high frequency amplifier and limiter .1 .1 1 2 4 3 5 8 am carrier is amplified and limited here 10k 51 50k 10k 1k 1k .1 600 1k + + 8 10 1 4 14 5 12 6 3 2 6.8k de-emphasis v o u t v out phase angle -90 90 0 sr00780 figure 7. am demodulator note: all resistor values are in w . 1k 1k +12vdc 1k 51 8 10 1 4 14 5 12 6 3 2 3.9k 3.9k phase 1 phase 2 51 51 6.8k mc1496 0.1 m f 0.1 m f r e r l r l i 5 +v o v o v c mc1596 v 8vdc sr00781 figure 8. phase comparator at 90 the cosine becomes zero, while being at maximum positive or maximum negative at 0 and 180 , respectively. the advantage of using the balanced modulator over other types of phase comparators is the excellent linearity of conversion. this configuration also provides a conversion gain rather than a loss for greater resolution. used in conjunction with a phase-locked loop, for instance, the balanced modulator provides a very low distortion fm demodulator. frequency doubler very similar to the phase detector of figure 8, a frequency doubler schematic is shown in figure 10. departure from figure 8 is primarily the removal of the low-pass filter . the output then contains the sum component which is twice the frequency of the input, since both input signals are the same frequency .
philips semiconductors application note AN189 balanced modulator/demodulator applications using the mc1496/1596 1988 may 5 8vdc average + vdc average vdc average vco input f = 90 f = 0 f = 180 sr00782 figure 9. phase detector voltages note: all resistor values are in w . 1k 1k +12vdc 1k 100 7 8 1 4 10 5 9 6 3 2 3.9k 3.9k 10k 51 6.8k mc1496 100 m f i 5 output mc1596 100 m f 100 m f 10k 100 100 50k balance 15vdc c2 c2 vdc 8 + + input 15mv rms sr00783 figure 10. low frequency doubler
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